This relates to integrated circuits and more particularly, to systems for designing logic circuitry on integrated circuit devices such as programmable integrated circuits.
Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit that performs custom logic functions. When the design process is complete, the computer-aided design tools generate configuration data. The configuration data is loaded into memory elements to configure the devices to perform the functions of the custom logic circuit. Memory elements are often formed using random-access-memory (RAM) cells. Because the RAM cells are loaded with configuration data during device programming, the RAM cells are sometimes referred to as configuration memory or configuration random-access-memory cells (CRAM).
Integrated circuits such as programmable integrated circuits often include millions of gates and megabits of embedded memory. The complexity of a large system requires the use of electronic design automation (EDA) tools to create and optimize a logic design for the system onto an integrated circuit (target device). The tools may perform logic synthesis operations to generate a gate-level description of the logic design for implementation on a target programmable logic device. Logic synthesis also performs technology mapping to map the gates onto logic elements (resources) that are available on the target programmable logic device. The logic elements are then physically placed and routed onto the target programmable device, while concurrently optimizing for timing, area, wiring, routing congestion, and power.
In practice, it is desirable for logic elements be placed adjacent to one another on the target programmable device without overlap or with minimal overlap. Overlapping logic elements can lead to increased complexity as well as other technical challenges when implementing the final overlap-free logic design, such that all legal placement rules are satisfied. In other cases, overlapping logic elements can render the logic elements inoperable.